The present invention relates in general to semiconductor device structures and their fabrication. More specifically, the present invention relates to the fabrication of a fin-type field effect transistor (FinFET) with equal spacers for n-type and p-type transistors.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. A complementary metal-oxide-semiconductor uses both n-type FETs and p-type FETs in the same device.
One particularly advantageous type of MOSFET is known generally as a fin-type field effect transistor (FinFET). A three-dimensional view of an exemplary FinFET 100 is shown in FIG. 1. The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional field effect transistor. FinFET 100 includes a semiconductor substrate 102, a shallow trench isolation (STI) layer 104, a fin 106 and a gate 114, configured and arranged as shown. Fin 106 includes a source region 108, a drain region 110 and a channel region 112, wherein gate 114 extends over the top and sides of channel region 112. For ease of illustration, a single fin is shown in FIG. 1. In practice, FinFET devices are fabricated having multiple fins formed on STI 104 and substrate 102. Substrate 102 may be silicon, and STI 104 may be an oxide (e.g., SiO2). Fin 106 may be silicon that has been enriched to a desired concentration level of germanium. Gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1). In contrast to a planar MOSFET, however, source 108, drain 110 and channel 112 are built as a three-dimensional bar on top of STI layer 104 and semiconductor substrate 102. The three-dimensional bar is the aforementioned “fin 106,” which serves as the body of the device. The gate electrode is then wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. The source and drain regions are the portions of the fin on either side of the channel that are not under the gate electrode. The dimensions of the fin establish the effective channel length for the transistor.
Typically, during the manufacture of a semiconductor, a POC liner is used to protect the source and drain epitaxial growth. Typically, the POC liner has been silicon nitride. A more efficient method of constructing a semiconductor, using selective nitride growth on conductor materials, is presented herein.